A semiconductor nonvolatile memory apparatus of a single-transistor-per-cell configuration which can collectively erase the stored information electrically is a flash memory. The flash memory has such a configuration that the area occupied for each bit is small and high integration is possible. For this reason, this memory has been closely watched recently and various research and development efforts are made actively on the structure and the method of driving it.
A first example that has thus far been suggested is a DINOR type described in "Symposium on VLSI Circuits Digest of Technical Papers", pp.97-98, 1993; a second example is a NOR type described in the same papers, pp.99-100, 1993; a third example is an AND type described in the same papers, pp.61-62, 1994; and a fourth example is a HICR type described in "International Electron Devices Meeting Tech. Dig.", pp.19-22.
With each of the above-mentioned types, at the time of the read operation, the word line potential is set to a source voltage Vcc and a low voltage of about 1 V is applied as a bit line potential to prevent weak electrons from being drawn, while information is read from memory cells by a sense amplifier circuit. Let the state in which electrons are stored in a floating gate be defined as an erase mode. In erase mode, the threshold voltage of the memory cell increases. Even if a word line is selected at the time of read operation, therefore, no drain current flows and the bit line potential is held at a precharge potential of 1 V. Let the state in which no electrons are injected (electrons are discharged) be defined as a write mode, on the other hand. In write mode, the threshold voltage value of the memory cell drops. When a word line is selected, therefore, a current begins to flow, and the bit line potential decreases below the precharge potential 1V. The bit line potential is amplified by a sense amplifier thereby to judge a "0" or a "1" state of the information.
A first example so far suggested is an AND type described in "International Electron Devices Meeting Tech. Dig." pp.991-993, 1992, and a second example is a HICR type described in the same papers, pp.19-22, 1993.
In each of these types, the operation of increasing the threshold voltage of a memory cell in the sector representing a unit of each word line is defined as an erase operation.
In the AND type described in "Symposium on VLSI Circuits Digest of Technical Papers", pp.61-62, 1994, a high positive voltage of 16 V is applied to a selected sector, i.e., a selected word line as an erase operation voltage, and the drain and source terminal voltages of the memory cell are set to the ground voltage Vss of 0 V. A voltage difference occurs between the channel and the floating gate of the memory cell in the selected sector, and the electrons in the channel are injected into the floating gate by the Fowler-Nordheim tunnel phenomenon. An erase operation thus is made possible for increasing the threshold voltage of the memory cell.
With the flash memories of the above-mentioned types, a read error is caused when the threshold voltage of the memory cell assumes a negative value. It is therefore necessary to control the threshold voltage of the memory cell not to assume a negative value. For this purpose, the write operation sequence shown in FIG. 29 is executed in the prior art. In the write operation for the AND type constituting the third prior art described above, for example, a unit write time is set for a memory cell group (sector) connected to a predetermined word line in a memory cell array and data are written collectively, after which the data are read from the memory cells. If there is any memory cell in which data are not sufficiently written, a rewrite operation (verify operation) is performed. The word line potential at the time of the verify operation for checking whether the threshold voltage of a memory cell has reached a write threshold voltage or not is set to 1.5 V, for example, as a value at which the threshold voltage of none of the memory cells of the memory cell group in the sector assumes a negative voltage, taking the expansion of the distribution of the write threshold voltage into consideration.
"Symposium on VLSI Technology Digest of Technical Papers" pp.83-84, 1993, discloses an erratic imperfection, a phenomenon in which the electrons in the floating gate are injected or discharged through a tunnel film making up an insulation film, and therefore the internal electric field of the tunnel film is strengthened with the trap level in the tunnel film charged to a positive voltage with the result that the electrons are locally apt to be discharged from the floating gate, or a phenomenon in which the trap level is charged or not charged to a positive voltage depending on the number of rewrite operations. The above-mentioned conventional techniques cannot detect an erratic imperfection that occurs during the write operation as shown in FIG. 26 and thus poses the problem that upon occurrence of an erratic imperfection, accurate information cannot be read out from the semiconductor nonvolatile memory apparatus.
The write operation according to each of the above-mentioned types is for decreasing the threshold voltage of a selected memory cell. The AND-type apparatus, as described in the related papers, comprises a sense latch circuit for performing the operation of latching the write data for each bit line of a memory cell and performs the write operations for each sector collectively. A negative voltage of -9 V is applied to the control gate, i.e., a word line of the memory cell, and the drain terminal voltage of the memory cell is set to 4 V for the selected cell and to 0 V for the non-selected cells according to the data of the sense latch circuit. A voltage difference occurs between the floating gate and the drain of the selected memory cell so that the electrons in the floating gate are drawn toward the drain by the Fowler-Nordheim tunnel phenomenon. In the non-selected memory cells, the voltage difference between the floating gate and the drain is so small that the electrons are prevented from being discharged from the floating gate.
In the write operation, on the other hand, the threshold voltage of the memory cells in the non-selected sectors slightly drops depending on the selected drain terminal voltage. In order to prevent this, a source voltage Vcc is applied to the non-selected word lines.
For the conventional semiconductor nonvolatile memory apparatus of AND type, the breakdown voltage of the MOS transistors making up the apparatus is required to be not less than 16 V providing a word line voltage not for the write operation but for the erase operation at which the potential difference is highest. In order to secure this breakdown voltage, the gate insulation film of each MOS transistor is increased to the thickness of not less than 25 nm, for example, to reduce the field strength applied to the gate oxide film while at the same time making a diffusion layer structure of a high breakdown voltage, and even when using a minimum rule of 0.4 .mu.m, the gate length is required to be 1.5 .mu.m or more, for example. As a result, the layout area of the MOS transistor is increased, thereby leading to the problem of an increased chip size of the semiconductor nonvolatile memory apparatus.
As such a flash memory, a flash memory of AND type is suggested in JP-A-7-176705, for example. FIG. 19 is a connection diagram of memory cells, and FIG. 20 is a schematic diagram showing a layout according to JP-A-7-176705 shown in FIG. 1. A plurality of memory cells are connected along the columns as a unit block. The drain of each memory cell is connected to a bit line through a MOS transistor, and the source of each memory cell is connected to a common source line through a MOS transistor. Also, the bit line is connected with a plurality of unit blocks. As shown in FIG. 20, a common source line is formed of a diffusion layer in the vertical direction between the bit lines as designated by L (SL), and further, is wired using a metal line M1 (SL) in the same layer as the bit lines in the direction parallel to a plurality of the bit lines.
With the conventional flash memory of AND type described above, the read operation and the verify operation for the threshold voltage of the memory cell after the rewrite operation are performed collectively for each sector of the memory cells connected to the word lines. In view of the fact that the common source line L (SL) is formed of a diffusion layer, a voltage effect occurs in the common source line L (SL) by the memory cell current flowing in the common source line L (SL) as shown in the equivalent circuit of a memory cell array of FIG. 53. Consequently, a substrate bias is effectively applied to the memory cells to change the threshold voltage thereof. The amount of change of the threshold voltage varies depending on the information pattern stored in each memory cell and the position of the memory cell. The subsource lines are formed also of a diffusion layer. Since a current of an amount corresponding to not more than a single memory cell flows, however, the variations in the threshold voltage of the memory cells of a sector are not caused.
FIG. 56 shows the threshold voltage dependency on the position of a memory cell on a bit line. The substrate bias has the greatest effect on a memory cell farther from the source line so that the threshold voltage of the memory cell is increased by the substrate bias. The substrate bias becomes maximum in the case where all the bits of the memory cell are write bits, i.e., in the case where the threshold voltage is so low that a cell current flows. The threshold voltage takes the lowest value, on the other hand, in the case where only one bit of the cell adjacent to the source line is a write cell. This threshold voltage difference .DELTA.Vth causes variations of the threshold voltage among the memory cells in the sector.
For reading the memory information, it is necessary to reduce the threshold voltage difference .DELTA. Vth and to stabilize the read operation. For this purpose, the common source line M1 (SL) shown in FIG. 20 is required for each 32 bit lines. This, however, poses the problem that the area of the memory array section increases by 3% or more.
In view of this, an object of the present invention is to provide an electrically-rewritable semiconductor nonvolatile memory apparatus and a computer system using such a memory apparatus, in which an operation sequence is newly set, the erratic phenomenon is suppressed in the apparatus and the rewrite resistance can be improved.
Another object of the invention is to provide an electrically-rewritable semiconductor nonvolatile memory apparatus and a computer system using such a memory apparatus, in which the maximum voltage for the erase operation of the electrically-rewritable nonvolatile memory apparatus is reduced to almost the same level as the maximum operating voltage for write operation thereby to reduce the chip size.
Still another object of the invention is to provide an electrically-rewritable semiconductor nonvolatile memory apparatus, in which the operation of reading information is stabilized for each sector, i.e., the variations in threshold voltage are reduced and further the apparatus area is also reduced.